SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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Careful control during fabrication is necessary to avoid this problem.
Define local skew, global skew, and deslgn skew. To store ‘1’, it is charged and to store ‘0’ it is discharged to ‘0’ volt. Write notes on functionality tests?
Zero gate voltage drain current Idss 6. An approach to fault analysis is known as fault sampling. Why is carry bypass Adder called so? Channeled gate array Channel less gate array Only the interconnect is customized Only the top few mask layers are customized The interconnect uses predefined No predefined areas are set aside answerz spaces between rows of base cells routing between cells.
What are the different levels of answer abstraction at physical design. The Device that conduct with zero gate bias.
What are the types of procedural assignments? What are the contents of the test architecture? Steps to ec254 metastability: Intra-assignment delay control 3. What are the steps involved in twin-tub process? These tests are usually used early in the design cycle to verify the functionality of the circuit. The load capacitance can be reduced to reduce delay this is achieved by using transistor of smaller and smaller dimension by feature generation technology.
Using faster flip flops which has narrower metastable window. Only the top few mask layer customized customized. The main advantage of transmission gate is that it eliminates the threshold voltage drop. Low input impedance 5. Give the steps inASIC design flow.
What are the advantages of silicon on insulator SOI process? Elmore delay model estimates the delay of a RC ladder as the sum over each node in the ladder of the resistance Rn 1 between that node and a supply multiplied by the capacitor on the nodes.
Help Center Find new research papers in: FPGAs can be used to implement a wjth circuit with more than 20, gates whereas a CPLD can implement circuits of upto about 20, equivalent gates. Explain the basic operation of a 2 phase dynamic circuit. The power dissipation is proportional to clock frequency Greater device leakage current: What is an antifuse? Click here to sign up. Eliminate logic switching that is not necessary for computation.
EC – VLSI Design TWO MARKS WITH ANSWERS | Manoharan K. –
What is pull down device? Which factors dominates the performance of a programmable shifter? It is used to convey information through the use of color code. Some of the important CAD tools are: Remember me on this computer. What is transmission gate?
EC VLSI Design Two Marks with Answers – Edition
Manufacturing tests verify that every gate and register in the chip functions correctly. Give the basic inverter circuit. One additional capacitor is explicitly fabricated for storage purpose. In the mealy state machine we can calculate the next state and output both from the input and state. Give the different types of ASIC. qnswers
What is a pull down device? The logic cells in a gate array are often called as macros. What are the categories of testing?
State the different operating regions for an MOS transistor. Vosi node or line to be faulted is set to 0 and then 1 and the test vector set is applied. What are the advantages of carry skip adder?
The carry skip adder is shown to be superior to constant width carry skip module the advantages being greater at high precisions. What is the full custom ASIC design?